1. Field
The embodiment generally relates to circuits restoring the shape of a pulse signal, and particularly relates to a circuit for reducing the jitter of a pulse signal.
2. Description of the Related Art
Due to the improvement of performance of information processing equipment such as communication apparatuses and servers used in communication trunk lines, it becomes necessary to increase the data rate of information transmission inside as well as between the equipments. For example, transmission speed needs to be improved by using higher frequency signals for signal transmission between devices and circuit blocks inside a chip, for signal transmission between chips such as between a processor chip and a memory chip like SRAM or DRAM, for signal transmission between boards, and for signal transmission between information apparatuses.
An increase in signal frequency, however, results in the signal waveform being distorted due to the attenuation of high frequency components resulting from the effect of the frequency characteristics of amplifiers and buffers as well as wire resistance inside a chip. Further, signal quality degrades due to crosstalk, ground bounce, and the like. Outside the chip, also, signal waveforms are distorted due to the frequency characteristics of coupling cables.
In order to compensate for the degradation of signal quality (i.e., the distortion of signal waveform), it is not sufficient to merely insert an amplifier (e.g., a limiting amplifier) for the purpose of restoring a signal level. This is because such amplifier cannot compensate for timing fluctuation (i.e., timing jitter). The restoration of signal timing is thus necessary in addition to the restoration of signal level. In order to restore signal quality inside a chip, generally, provision is made to arrange flip-flops operating with a small-jitter clock along the signal transmission lines, so that these flip-flops restore the level and timing of signals.
When the signal frequency becomes as high as several GHz to several tens of GHz, however, it becomes difficult to design and manufacture flip-flops that can properly operate at such high frequency. If flip-flops satisfying such needs are successfully manufactured, the size and power consumption would be prohibitively large. A level-restoring circuit (repeater) may be implemented as a combination of an ordinary high-speed I/O receiver and transmitter. With such configuration, the circuit size will also be prohibitively large, and the cost will increase.
The operation by a flip-flop restoring the level and timing of a signal is comprised of two steps, i.e., the sampling of an input signal at clock-edge timing and the restoring of the level of the input signal by use of a restoration-type amplifier or limiting amplifier. In this case, almost all the energy of the input signal is discarded, and the restoring-type amplifier reconstructs its output signal almost from scratch. Accordingly, the restoration of a signal level by use of a flip-flop is, in principle, an act of wastefully consuming electric power. Further, the sample circuit for sampling the input signal into the flip-flop needs to have the sampling interval thereof set sufficiently shorter than the clock cycle, which makes it difficult to increase operating frequency.
Accordingly, there is a need for a jitter reduction circuit that can restore the level and timing of signal efficiently in terms of power consumption, circuit size, and cost even when higher signal frequency is used.
[Patent Document 1] Japanese Patent Application Publication No. 2001-44976